(1) Field of the Invention
The present invention generally relates to cross-point type switches used in an ATM (Asynchronous Transfer Mode) system or a high-bit-rate packet communication system of a broadband ISDN (Integrated Services Digital Network). More specifically, the present invention is concerned with an arrangement for controlling a switching operation on a switch, such as a cross-point type switch, so that input data are switched in order of receipt of the input data.
(2) Description of the Prior Art
FIG. 1 shows a conventional cross-point type switch. The cross-point type switch shown in FIG. 1 is composed of an input port group 1 having N input ports (N is an integer larger than 2), an output port group 2 having N output ports, a memory 3, N route setting units 4, and an output controller 8. Memories are arranged in rows and columns. More specifically, the memories are provided at cross points of input lines running in the row direction and output lines running in the column direction. Each of the memories may comprise for example, an FIFO (First-In First-Out) memory.
The routing units 4 receive data, such as ATM data, received via the input port group 1, and determine paths to which the received data should be output. For example, if data received via the input port #1 is requested to be transferred to the output port #2, the received data is stored in the memory located at the cross point of the input line connected to input port #1 and the output line connected to output port #2. The output controller 8 controls the memory 3 so that each of the output lines connected to the output port 2 carries, at one time, only one data block (i.e., a cell or packet) transferred from any one of input ports #1-#N. That is, the output controller 8 prevents two or more data blocks from being transferred to one of the output lines at one time.
FIG. 2 shows a procedure by which the output controller 8 controls the memory 3. More specifically, FIG. 2 shows N FIFO memories 3.sub.11 -3.sub.1N arranged in the first column, an output-port controller 8.sub.1, which, a part of the output controller 8, and a multiplexer 25. The FIFO memories 3.sub.11 -3.sub.1N are connected to the multiplexer 25, which is connected to output port #1. When each of the FIFO memories 3.sub.11 -3.sub.1N receives data to be transferred to the corresponding output port, each FIFO memory sets an empty flag EF to zero when the FIFO memory has been filled with data and there is no available storage area therein. It will now be assumed that the controller 8.sub.1 controls the memories 3.sub.11 -3.sub.1N so that data is transferred to the multiplexer 25. The controller 8.sub.1 sequentially determines whether or not the empty flags EF received from the FIFO memories 3.sub.11 -3.sub.1N are equal to zero. Then the controller 8.sub.1 controls the multiplexer 25 so that data from the FIFO memories from which the empty flags EF are equal to zero have been output and sequentially transferred to output port #1.
However, the conventional memory control procedure has the following disadvantages. The controller 8.sub.1 sequentially accesses input ports #1-#N one by one, in sequential order, to determine whether or not the FIFO memory being accessed has any available storage area. It should be noted that the above sequential access to the FIFO memories is carried out without considering how full each FIFO memory is. Hence, there is a possibility that some FIFO memories connected to a certain output port are full and hence it takes a long time to read out all the data therefrom.